`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:24:59 11/04/2014
// Design Name:   Rx
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/Xilin/UART/RxTest.v
// Project Name:  UART
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Rx
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RxTest;

	// Inputs
	reg data;
	reg tick;

	// Outputs
	wire [7:0] Data_Out;
	wire rx_done;

	// Instantiate the Unit Under Test (UUT)
	Rx uut (
		.data(data), 
		.tick(tick), 
		.Data_Out(Data_Out), 
		.rx_done(rx_done)
	);

	initial begin
		// Initialize Inputs
		data = 1;
		tick = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#320
		data = 0;	//bit de start
		#320
		data = 1;	//Primer bit de datos
		#320
		data = 0;	//Segundo bit de datos
		#320
		data = 1;	//tercer bit de datos
		#1280
		data = 1;	//Bit de stop
		
	end
 always begin 
	#10;
	tick = ~tick;     
 end
endmodule

